Method for manufacturing semiconductor substrate

ABSTRACT

One surface of a single crystal semiconductor substrate is irradiated with ions to form a damaged region in the single crystal semiconductor substrate. An insulating layer is formed over the one surface of the single crystal semiconductor substrate. A surface of a substrate having an insulating surface and a surface of the insulating layer are disposed in contact with each other to bond the substrate having the insulating surface and the single crystal semiconductor substrate to each other. Heat treatment is performed to divide the single crystal semiconductor substrate along the damaged region and to form a semiconductor layer over the substrate having the insulating surface. One surface of the semiconductor layer is irradiated with light from a flash lamp under conditions where the semiconductor layer is not melted, to repair a defect.

BACKGROUND OF THE INVENTION

1. Field of the Invention

A technical field of the present invention relates to a method formanufacturing a semiconductor substrate.

2. Description of the Related Art

In recent years, semiconductor devices formed using an SOI (silicon oninsulator) substrate, instead of a bulk silicon substrate, have beendeveloped. By utilizing the features of a thin single crystal siliconlayer formed over an insulating layer, transistors in a semiconductordevice can be completely isolated from each other, and further, fullydepleted transistors can be formed. Accordingly, a semiconductorintegrated circuit with high added values such as high integration, highspeed driving, and low power consumption can be realized.

As a method for manufacturing an SOI substrate, a so-calledhydrogen-ion-implantation separation method is known. A typical processof the method will be described below.

First, hydrogen ions are implanted into a silicon substrate to form adamaged region at a predetermined depth from the surface. Next, asilicon oxide film is formed by oxidation of another silicon substratewhich serves as a base substrate. After that, the silicon substratewhere the damaged region is formed and the silicon oxide film on theother silicon substrate are firmly attached to each other to bond thetwo silicon substrates. Then, heat treatment is performed, whereby oneof the silicon substrates is separated along the damaged region.

In the aforementioned method, a silicon substrate is used as a basesubstrate, and as its application, there is a known method for forming asingle crystal silicon layer over a glass substrate (for example, seeReference 1). Note that in Reference 1, a separation plane ismechanically polished in order to remove a defect formed by ionimplantation or a step on the separation plane.

-   [Reference 1] Japanese Published Patent Application No. H11-097379

SUMMARY OF THE INVENTION

In the case where a single crystal semiconductor layer is formed byusing a method in which a single crystal semiconductor substrate isirradiated with ions, the ion irradiation leads to an increase ofdefects in the single crystal semiconductor layer. In the case wheremany such defects exist in a single crystal semiconductor layer, asemiconductor element manufactured using this single crystalsemiconductor layer has poorer characteristics; for example, defectlevels are easily generated at the interface with a gate insulatinglayer. Further, in the case where many defects exist in a single crystalsemiconductor layer, original characteristics of the single crystalsemiconductor cannot be obtained.

As a solution to the above problems, for example, recrystallization byheat treatment (heating in thermal equilibrium) can be given. However,heat treatment at a high temperature (e.g., 800° C. or higher) is notappropriate as treatment on a single crystal semiconductor layer formedover a glass substrate. This is because a glass substrate has an issueabout allowable temperature limit.

As an alternative method, a method in which a single crystalsemiconductor layer is irradiated with laser light is given, forexample. By irradiation with laser light, only the single crystalsemiconductor layer can be selectively melted, whereby defects can bereduced. As the laser light, pulsed laser light is typically used. Thepulsed laser light has the advantage that light intensity that is neededfor melting can be obtained more easily than in the case of usingcontinuous-wave laser light.

Here, in the case of irradiating a single crystal semiconductor layerwith laser light, there is a problem in that characteristics of thesingle crystal semiconductor layer are lowered in a region irradiatedwith an edge portion of the laser light. This is because a melted regionand an unmelted region are mixed in that region, and therefore, adistortion is easily generated in a crystal structure at a boundarybetween the melted region and the unmelted region. Then, as a result ofgeneration of such a distortion, a protruding object (projection) iscreated on the surface of the semiconductor layer and a crystal grainboundary is formed. As a method for solving this problem, enlargement ofa laser light irradiation area can be considered so as to be able tomelt a whole area of a single crystal semiconductor layer, for example.However, it is very difficult to obtain laser light having a lightintensity that enables a large-area semiconductor layer to be uniformlymelted.

In view of the foregoing problems, an object of an embodiment of theinvention disclosed in this specification and the like (including atleast the specification, the claims, and the drawings) is to improvecharacteristics of a semiconductor layer without lowering productivityof a semiconductor substrate. Another object is to suppress in-planevariation of a semiconductor layer and to obtain a semiconductor layerhaving uniform characteristics.

In one embodiment of the disclosed invention, a surface of asemiconductor layer is irradiated with light from a flash lamp to repairdefects in the semiconductor layer. In that case, the semiconductorlayer is not melted (or the planarity of the surface of thesemiconductor layer is not changed). The time of irradiation with thelight from the flash lamp (pulse width) is 10 μs or more (preferably 10μs to 100 ms, more preferably 100 μs to 10 ms). The light from the flashlamp is preferably light having a continuous spectrum in a visible lightregion (at least from 400 nm to 700 nm), that is, white light.

A feature of one method for manufacturing a semiconductor substratewhich is one embodiment of the disclosed invention is as follows. Onesurface of a single crystal semiconductor substrate is irradiated withions to form a damaged region in the single crystal semiconductorsubstrate. An insulating layer is formed over the one surface of thesingle crystal semiconductor substrate. A surface of a substrate havingan insulating surface and a surface of the insulating layer are disposedin contact with each other to bond the substrate having the insulatingsurface and the single crystal semiconductor substrate to each other.Heat treatment is performed to divide the single crystal semiconductorsubstrate along the damaged region and to form a semiconductor layerover the substrate having the insulating surface. One surface of thesemiconductor layer is irradiated with light from a flash lamp underconditions where the semiconductor layer is not melted, to repair adefect.

A feature of another method for manufacturing a semiconductor substratewhich is one embodiment of the disclosed invention is as follows. Onesurface of a single crystal semiconductor substrate is irradiated withions to form a damaged region in the single crystal semiconductorsubstrate. A first insulating layer is formed over the one surface ofthe single crystal semiconductor substrate. A second insulating layer isformed over one surface of a substrate having an insulating surface. Asurface of the second insulating layer and a surface of the firstinsulating layer are disposed in contact with each other to bond thesubstrate having the insulating surface and the single crystalsemiconductor substrate to each other. Heat treatment is performed todivide the single crystal semiconductor substrate along the damagedregion and to form a semiconductor layer over the substrate having theinsulating surface. One surface of the semiconductor layer is irradiatedwith light from a flash lamp under conditions where the semiconductorlayer is not melted, to repair a defect.

A feature of another method for manufacturing a semiconductor substratewhich is one embodiment of the disclosed invention is as follows. Aninsulating layer is formed over one surface of a single crystalsemiconductor substrate. One surface of the insulating layer isirradiated with ions to form a damaged region in the single crystalsemiconductor substrate. A surface of a substrate having an insulatingsurface and the surface of the insulating layer are disposed in contactwith each other to bond the substrate having the insulating surface andthe single crystal semiconductor substrate to each other. Heat treatmentis performed to divide the single crystal semiconductor substrate alongthe damaged region and to form a semiconductor layer over the substratehaving the insulating surface. One surface of the semiconductor layer isirradiated with light from a flash lamp under conditions where thesemiconductor layer is not melted, to repair a defect.

A feature of another method for manufacturing a semiconductor substratewhich is one embodiment of the disclosed invention is as follows. Afirst insulating layer is formed over one surface of a single crystalsemiconductor substrate. One surface of the first insulating layer isirradiated with ions to form a damaged region in the single crystalsemiconductor substrate. A second insulating layer is formed over onesurface of a substrate having an insulating surface. A surface of thesecond insulating layer and the surface of the first insulating layerare disposed in contact with each other to bond the substrate having theinsulating surface and the single crystal semiconductor substrate toeach other. Heat treatment is performed to divide the single crystalsemiconductor substrate along the damaged region and to form asemiconductor layer over the substrate having the insulating surface.One surface of the semiconductor layer is irradiated with light from aflash lamp under conditions where the semiconductor layer is not melted,to repair a defect.

In the above description, the expression “conditions where thesemiconductor layer is not melted” refers to conditions where volumemovement resulting from melting does not occur, but the expression doesnot exclude conditions where instantaneous melting occurs while volumemovement does not occur, conditions where microscopic bond rearrangementoccurs, and the like. In this sense, the above expression “underconditions where the semiconductor layer is not melted” can be replacedwith the expression “under conditions where the planarity of the surfaceof the semiconductor layer is not changed.” In other words, theintensity of the light from the flash lamp may be controlled such thatthe unevenness of the surface of the semiconductor layer does notchange.

Note that in the above methods, planarization treatment is preferablyperformed on the semiconductor layer before or after the irradiationwith the light from the flash lamp. Here, etching treatment can beemployed as the planarization treatment. Alternatively, laser lightirradiation treatment may be employed unless it causes a variation incharacteristics.

In the above methods, the time of irradiation with the light from theflash lamp is preferably 10 μs or more. In addition, the light from theflash lamp preferably has a continuous spectrum in a wavelength rangefrom 400 nm to 700 nm. As such a flash lamp, a xenon lamp can be used,for example.

Note that in the above methods, during the irradiation with the lightfrom the flash lamp, the temperature of the substrate having theinsulating surface is preferably kept at 300° C. or higher.

In one embodiment of the disclosed invention, light from a flash lamp(hereinafter also referred to as flash lamp light) is used to repairdefects of a semiconductor layer without melting the semiconductorlayer. Thus, compared to the case of using laser light and melting asemiconductor layer, productivity can be drastically improved. Inaddition, since a semiconductor layer is not melted, a crystal grainboundary and the like resulting from generation of a melted region andan unmelted region are not produced. Thus, in-plane variation of asemiconductor layer can be reduced, and a semiconductor layer havingfavorable and uniform characteristics can be obtained. Furthermore,compared to heating in thermal equilibrium with a furnace or the like,treatment can be efficiently performed in an extremely short time. Thatis, a large-area substrate having favorable and uniform characteristicscan be provided extremely efficiently. Note that when a semiconductorlayer is irradiated with laser light to improve its characteristics,linear pulsed laser light having a beam spot of about 0.5 mm×300 mm isnormally used. This is because light intensity sufficient for partialmelting of the semiconductor layer is needed. On the other hand, in thepresent invention, flash lamp light enables a large area to be treatedat a time.

Note that a semiconductor layer having favorable characteristics can beformed without being melted because a semiconductor layer which isseparated from a single crystal semiconductor substrate (which may behereinafter referred to as a “quasi-single-crystal semiconductor layer”for convenience) is used as the semiconductor layer. A semiconductorlayer which is separated from a single crystal semiconductor substrate(a quasi-single-crystal semiconductor layer) has a basic structuresimilar to that of a single crystal semiconductor layer and differs froma single crystal semiconductor layer simply by the presence of a largenumber of defects. In other words, if defects can be effectivelyrepaired, extremely high characteristics like those of a single crystalsemiconductor can also be obtained in the case of using a non-meltdefect repair process.

Note that in a process which requires melting of a semiconductor layer,such as in the case of laser light irradiation, there is a problem inthat the range of optimal power densities is narrow. On the other hand,in one embodiment of the disclosed invention, melting of a semiconductorlayer is not needed; thus, the range of optimal power densities is broadand that is extremely advantageous in a manufacturing process of asemiconductor substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1F are diagrams illustrating a method for manufacturing asemiconductor substrate.

FIGS. 2A to 2C are diagrams illustrating a method for manufacturing asemiconductor substrate.

FIGS. 3A to 3D are diagrams illustrating a method for manufacturing asemiconductor substrate.

FIGS. 4A to 4D are diagrams illustrating a method for manufacturing asemiconductor substrate.

FIGS. 5A to 5E are diagrams illustrating a method for manufacturing asemiconductor substrate.

FIGS. 6A to 6C are diagrams illustrating a method for manufacturing asemiconductor substrate.

FIGS. 7A and 7B are diagrams illustrating an irradiation method with aflash lamp.

FIGS. 8A to 8D are diagrams illustrating a manufacturing process of asemiconductor device.

FIGS. 9A to 9D are diagrams illustrating a manufacturing process of asemiconductor device.

FIGS. 10A and 10B are a cross-sectional view of a semiconductor deviceand a plan view thereof, respectively.

FIGS. 11A and 11B are graphs showing a dependance of Raman peak on flashlamp light intensity and a dependance of full width at half maximum ofRaman peak on flash lamp light intensity.

FIGS. 12A and 12B are diagrams showing a condition of surface unevennessof a silicon layer before flash lamp light irradiation.

FIGS. 13A and 13B are diagrams showing a condition of surface unevennessof a silicon layer after flash lamp light irradiation.

FIGS. 14A and 14B are diagrams each illustrating a state at the time oflamp light irradiation.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments will be hereinafter described in detail with reference tothe attached drawings. Note that the present invention is not limited tothe description in Embodiments given below, and it is easily understoodby those skilled in the art that the mode and details of the inventiondisclosed in this specification and the like can be changed in variousways without deviating from the spirit of the invention. In addition,structures in different embodiments can be implemented in combination asappropriate. Note that the same portions or portions having a similarfunction are denoted by the same reference numerals, and repetitivedescription thereof is omitted. In addition, the semiconductor device inthis specification refers to all devices that operate by utilizingsemiconductor characteristics.

Embodiment 1

In Embodiment 1, a method for manufacturing a semiconductor substratewhich is one embodiment of the disclosed invention will be describedwith reference to FIGS. 1A to 1F and FIGS. 2A to 2C.

First, a base substrate 100 is prepared (see FIG. 1A). As the basesubstrate 100, a substrate having an insulating surface, such as avisible light transmitting glass substrate used for a liquid crystaldisplay device or the like, can be used, for example. As a glasssubstrate, a substrate having a strain point of 580° C. or higher(preferably, 600° C. or higher) may be used. Further, it is preferablethat the glass substrate be a non-alkali glass substrate. As a materialof the non-alkali glass substrate, a glass material such asaluminosilicate glass, aluminoborosilicate glass, or barium borosilicateglass is used, for example.

Note that as the base substrate 100, as well as a glass substrate, asubstrate having an insulating surface, such as a ceramic substrate, aquartz substrate, or a sapphire substrate, a substrate which is formedfrom a semiconductor material such as silicon, a substrate which isformed from a conductor such as metal or stainless steel, or the likecan also be used.

Although not described in this embodiment, an insulating layer may beformed over a surface of the base substrate 100. By providing theinsulating layer, even in the case where impurities (such as an alkalimetal or an alkaline earth metal) are included in the base substrate100, the impurities can be prevented from being diffused into asemiconductor layer. The insulating layer may have either a single-layerstructure or a stacked structure. As a material of the insulating layer,silicon oxide, silicon nitride, silicon oxynitride, silicon nitrideoxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminumnitride oxide, or the like can be given.

Note that in this specification and the like, an oxynitride refers to asubstance that contains more oxygen (atoms) than nitrogen (atoms). Forexample, a silicon oxynitride is a substance including oxygen, nitrogen,silicon, and hydrogen in ranges of 50 at. % to 70 at. %, 0.5 at. % to 15at. %, 25 at. % to 35 at. %, and 0.1 at. % to 10 at. %, respectively. Anitride oxide refers to a substance that contains more nitrogen (atoms)than oxygen (atoms). For example, a silicon nitride oxide is a substanceincluding oxygen, nitrogen, silicon, and hydrogen in ranges of 5 at. %to 30 at. %, 20 at. % to 55 at. %, 25 at. % to 35 at. %, and 10 at. % to25 at. %, respectively. Note that the above-mentioned ranges areobtained by measurement using Rutherford backscattering spectrometry(RBS) or hydrogen forward scattering (HFS). Moreover, the total of thepercentages of the constituent elements does not exceed 100 at. %.

Next, a single crystal semiconductor substrate 110 is prepared (see FIG.1B). As the single crystal semiconductor substrate 110, for example, asemiconductor substrate formed from an element belonging to Group 4 ofthe periodic table, such as silicon, germanium, silicon-germanium, orsilicon carbide, can be used. Needless to say, a substrate formed from acompound semiconductor such as gallium arsenide or indium phosphide maybe used. In this embodiment, as the single crystal semiconductorsubstrate 110, a single crystal silicon substrate is used. Althoughthere is no limitation on the size and the shape of the single crystalsemiconductor substrate 110, a circular semiconductor substrate of 8inches (200 mm) in diameter, 12 inches (300 mm) in diameter, 18 inches(450 mm) in diameter, or the like, for example, may be processed into arectangular shape and the processed substrate may be used. Asemiconductor substrate of more than 20 inches can also be used in someapplications. In this specification, the term “single crystal” means acrystal which has a crystal structure with certain regularity and inwhich crystal axes are aligned in the same direction in any part of thecrystal.

After the single crystal semiconductor substrate 110 is cleaned, aninsulating layer 112 is formed over a surface of the single crystalsemiconductor substrate 110. The insulating layer 112 is not necessarilyneeded. However, it is preferable to provide the insulating layer 112 inorder to prevent contamination of the single crystal semiconductorsubstrate 110, damage to the surface of the single crystal semiconductorsubstrate 110, etching of the surface of the single crystalsemiconductor substrate 110, and the like due to later ion irradiation.The thickness of the insulating layer 112 may be approximately 1 nm to400 nm.

As a material of the insulating layer 112, an insulating materialcontaining silicon or germanium as a component, such as silicon oxide,silicon nitride, silicon oxynitride, silicon nitride oxide, germaniumoxide, germanium nitride, germanium oxynitride, or germanium nitrideoxide, can be used. Further, a metal oxide such as aluminum oxide,tantalum oxide, or hafnium oxide, a metal nitride such as aluminumnitride, a metal oxynitride such as aluminum oxynitride, or a metalnitride oxide such as aluminum nitride oxide may also be used. Theinsulating layer 112 can be formed by a CVD method, a sputtering method,a method using oxidation (or nitridation) of the single crystalsemiconductor substrate 110, or the like.

Next, the single crystal semiconductor substrate 110 is irradiated withan ion beam 130 including ions accelerated by an electric field throughthe insulating layer 112, so that a damaged region 114 is formed in thesingle crystal semiconductor substrate 110 in a region at apredetermined depth from the surface thereof (see FIG. 1C). The depth atwhich the damaged region 114 is formed can be controlled by accelerationenergy and incident angle of the ion beam 130. The damaged region 114 isformed in a region at a depth equal to or substantially equal to theaverage penetration depth of the ions.

The thickness of a semiconductor layer which is separated from thesingle crystal semiconductor substrate 110 is determined by the depth atwhich the damaged region 114 is formed. The depth at which the damagedregion 114 is formed is 20 nm to 500 nm, preferably 30 nm to 200 nm,from the surface of the single crystal semiconductor substrate 110.

When the single crystal semiconductor substrate 110 is irradiated withions, an ion implantation apparatus or an ion doping apparatus can beused. In an ion implantation apparatus, a source gas is excited toproduce ions, the produced ions are mass-separated, and a process objectis irradiated with ions having a predetermined mass. In an ion dopingapparatus, a process gas is excited to produce ions, and a processobject is irradiated with the produced ions without mass separation.Note that in an ion doping apparatus provided with a mass separator, ionirradiation involving mass separation can also be performed as in an ionimplantation apparatus.

The ion irradiation step in the case of using an ion doping apparatuscan be performed under conditions, for example, at an accelerationvoltage of 5 kV to 100 kV (preferably 30 kV to 80 kV), with a dose of6×10¹⁵ ions/cm² to 4×10¹⁶ ions/cm², and with a beam current density of 2μA/cm² or more (preferably 5 μA/cm² or more, more preferably 10 μA/cm²or more).

In the case of using an ion doping apparatus, a gas containing hydrogencan be used as a source gas for the ion irradiation step. With the gascontaining hydrogen, H⁺, H₂ ⁺, and H₃ ⁺ can be produced as ions. In thecase where the gas containing hydrogen is used as a source gas, it ispreferable to perform irradiation with a large number of H₃ ⁺.Specifically, the proportion of H₃ ⁺ with respect to the total amount ofH⁺, H₂ ⁺, and H₃ ⁺ in the ion beam 130 is set to 70% or higher(preferably 80% or higher). By increasing the proportion of H₃ ⁺ in thismanner, the damaged region 114 can be made to contain hydrogen at aconcentration of 1×10²⁰ atoms/cm³ or more. An increase in the proportionof H₃ ⁺ and local inclusion of a large number of ions in the damagedregion 114 facilitate division along the damaged region 114. Inaddition, by irradiation with a large number of H₃ ⁺, ion irradiationefficiency is improved compared to the case of irradiation with H⁺ or H₂⁺. That is, the time needed for the irradiation can be shortened.

In the case of using an ion implantation apparatus, it is preferable toperform irradiation with H₃ ⁺ through mass separation. Of course,irradiation with H⁺ or H₂ ⁺ may be performed. Note that in the case ofusing an ion implantation apparatus, ion irradiation efficiency may belower than in the case of using an ion doping apparatus becauseirradiation is performed with selected ions.

As a source gas used for the ion irradiation step, as well as a gascontaining hydrogen, one or more kinds of gases selected from noblegases such as helium and argon, halogen gases typified by a fluorine gasand a chlorine gas, and halogen compound gases such as a fluorinecompound gas (e.g., BF₃) can be used. In the case where helium is usedas a source gas, the ion beam 130 with a high proportion of He⁺ ions canbe produced without mass separation. By using that ion beam 130, thedamaged region 114 can be efficiently formed.

Further, the damaged region 114 can also be formed by performing the ionirradiation step plural times. In this case, a different source gas maybe used for each of the ion irradiation steps or the same source gas maybe used for the ion irradiation steps. For example, ion irradiation canbe performed using a gas containing hydrogen as a source gas after ionirradiation is performed using a noble gas as a source gas.Alternatively, ion irradiation can be performed using a halogen gas or ahalogen compound gas, and then, ion irradiation can be performed using agas containing hydrogen.

After the damaged region 114 is formed, the insulating layer 112 isremoved and an insulating layer 116 is newly formed (see FIG. 1D). Here,the insulating layer 112 is removed because there is a high possibilitythat the insulating layer 112 may be damaged in the ion irradiationstep. If damage of the insulating layer 112 does not cause any problems,it is not necessary to remove the insulating layer 112. In this case,the insulating layer 116 may be newly formed over the insulating layer112, or a structure in which the insulating layer 116 is not formed maybe employed.

As a material of the insulating layer 116, an insulating materialcontaining silicon or germanium as a component, such as silicon oxide,silicon nitride, silicon oxynitride, silicon nitride oxide, germaniumoxide, germanium nitride, germanium oxynitride, or germanium nitrideoxide, can be used. Further, a metal oxide such as aluminum oxide,tantalum oxide, or hafnium oxide, a metal nitride such as aluminumnitride, a metal oxynitride such as aluminum oxynitride, or a metalnitride oxide such as aluminum nitride oxide may also be used. As amethod for forming the insulating layer 116, a CVD method, a sputteringmethod, a method using oxidation (or nitridation) of the single crystalsemiconductor substrate 110, or the like can be given. Note that theinsulating layer 116 has a single-layer structure in this embodiment;however, one embodiment of the disclosed invention is not interpreted asbeing limited thereto. The insulating layer 116 can have a stackedstructure of two or more layers.

Since the insulating layer 116 is a layer for bonding, the surfacethereof preferably has high planarity. For example, a layer with asurface having an arithmetic mean roughness of 0.6 nm or less(preferably 0.3 nm or less) and a root-mean-square roughness of 0.7 nmor less (preferably 0.4 nm or less) is formed. As such an insulatinglayer 116, a silicon oxide film formed by a chemical vapor depositionmethod using an organosilane gas can be used, for example. Note that thestructure illustrated in FIG ID is hereinafter referred to as asubstrate 140 for convenience.

Then, the base substrate 100 and the substrate 140 are bonded to eachother (see FIG. 1E). Specifically, surfaces of the base substrate 100and the substrate 140 (the insulating layer 116) are cleaned by a methodsuch as ultrasonic cleaning (including so-called megasonic cleaning witha frequency of 50 kHz to 5 MHz) and subjected to treatment using achemical solution which provides hydrophilic groups (such as ozonewater, a mixture of ammonium water and a hydrogen peroxide solution (andwater), or another oxidizing agent). Then, the surfaces of the basesubstrate 100 and the substrate 140 are disposed in contact with eachother and pressure is applied thereto. As treatment performed on thesurfaces of the base substrate 100 and the substrate 140, as well as thetreatment using a chemical solution, oxygen plasma treatment can begiven, for example.

Since it is considered that bonding involves van der Waals' force,hydrogen bonding, or the like, a method which can make the best of theseprinciples is preferably used. For example, before bonding, the surfacesof the base substrate 100 and the substrate 140 are preferably madehydrophilic by being subjected to treatment with a chemical solutionwhich provides hydrophilic groups or oxygen plasma treatment asmentioned above. By this treatment, hydrophilic groups are provided tothe surfaces of the base substrate 100 and the substrate 140;accordingly, many hydrogen bonds can be formed at the bonding interface.That is, bonding strength can be increased.

The atmosphere at the time of bonding can be an air atmosphere, an inertatmosphere such as a nitrogen atmosphere, an atmosphere containingoxygen or ozone, or a reduced-pressure atmosphere. By performing bondingin the inert atmosphere or the atmosphere containing oxygen or ozone,the hydrophilic groups provided to the surfaces of the base substrate100 and the substrate 140 can be effectively utilized for bonding.Alternatively, bonding can be performed in a reduced-pressureatmosphere. In this case, since the effect of contaminants in theatmosphere can be made small, the bonding interface can be kept clean.In addition, trapping of air between the substrates in bonding can bereduced.

In this embodiment, the process of forming a semiconductor layer bybonding one substrate 140 to one base substrate 100 is described;however, one embodiment of the disclosed invention is not limitedthereto. For example, a plurality of semiconductor layers may be formedby bonding a plurality of substrates 140 to one base substrate 100.

Next, heat treatment is performed on the base substrate 100 and thesubstrate 140 which have been bonded to each other, to strengthen thebond. The heat treatment is performed as immediately as possible afterthe bonding. This is because, in the case where the substrates aretransported after the bonding and before the heat treatment, there is ahigh possibility that the substrate 140 may be detached due to a sag ofthe base substrate 100.

The temperature of the above heat treatment needs to be a temperaturewhich is equal to or lower than an allowable temperature limit of thebase substrate and does not cause division in the substrate 140(division along the damaged region 114). For example, the temperaturecan be 150° C. to 450° C., preferably 200° C. to 400° C. The treatmenttime is preferably 1 minute to 10 hours (more preferably 3 minutes to 3hours), but optimal conditions can be appropriately determined from therelationship between the treatment speed and the bonding strength. Inthis embodiment, the heat treatment is performed at 200° C. for twohours. Alternatively, heating can be locally performed by irradiatingonly a region of the substrates, at which bonding is performed, withmicrowaves.

Next, the substrate 140 is divided into a single crystal semiconductorsubstrate 142, and the insulating layer 116 and a semiconductor layer118 (see FIG. 1F). Division of the substrate 140 is conducted by heattreatment. The temperature of the heat treatment can be set inconsideration of the allowable temperature limit of the base substrate100. For example, when a glass substrate is used as the base substrate100, the temperature of the heat treatment is preferably 400° C. to 650°C. Note that the upper limit of the temperature of the heat treatmentcan be appropriately set depending on heat resistance of the basesubstrate 100. For example, if the base substrate 100 is resistant toheat treatment at temperatures up to 750° C., the heat treatment may beperformed at a temperature of 750° C. or lower. Note that in thisembodiment, the heat treatment is performed at 600° C. for two hours.

By the above-described heat treatment, the volume of microvoids formedin the damaged region 114 is changed, whereby a crack is generated inthe damaged region 114. As a result, the single crystal semiconductorsubstrate 110 is divided along the damaged region 114. Since theinsulating layer 116 is bonded to the base substrate 100, thesemiconductor layer 118 separated from the single crystal semiconductorsubstrate 110 remains over the base substrate 100. Further, since thebonding interface between the base substrate 100 and the insulatinglayer 116 is heated by this heat treatment, a covalent bond is formed atthe bonding interface so that the bonding force between the basesubstrate 100 and the insulating layer 116 is further improved. Thesingle crystal semiconductor substrate 142 can be utilized again afterthe surface thereof is planarized.

In the above-described manner, a semiconductor substrate including thesemiconductor layer 118 over the base substrate 100 is formed (see FIG.2A). The semiconductor substrate has a structure where the insulatinglayer 116 and the semiconductor layer 118 are sequentially stacked overthe base substrate 100.

Defects due to the ion irradiation step or the division step exist inthe semiconductor layer 118 formed as described above. If thesemiconductor layer 118 has many defects, characteristics as a singlecrystal semiconductor cannot be exhibited, and performance andreliability of a semiconductor element are adversely affected; forexample, the localized state density at the interface between thesemiconductor layer 118 and the gate insulating layer is increased.Therefore, defect reduction treatment is performed on the semiconductorlayer 118.

In this embodiment, defect reduction in the semiconductor layer 118 isachieved by irradiating the semiconductor layer 118 with flash lamplight 132. More specifically, a whole area of the semiconductor layer118 is irradiated with the flash lamp light 132 (see FIG. 2B). In thatcase, the light intensity of the flash lamp light is set such that thesemiconductor layer 118 is not melted (or such that the planarity of thesurface of the semiconductor layer is not changed). For example, whenthe semiconductor layer 118 has a thickness of about 100 nm, the lightintensity of the flash lamp light may be set to about 0.1 J/cm² to 300J/cm² (preferably 1 J/cm² to 30 J/cm²). Note that the optimal lightintensity of the flash lamp light varies depending on the thickness ofthe semiconductor layer 118 or the like; thus, there is no need for thelight intensity to be interpreted as being limited to the range givenhere. The time of irradiation with the flash lamp light (pulse width) is10 μs or more (preferably 10 μs to 100 ms, more preferably 100 μs to 10ms). During the irradiation with the flash lamp light 132, thetemperature of the base substrate 100 is preferably kept at 300° C. orhigher (more preferably 500° C. or higher). Accordingly, defect repaircan be performed effectively.

Note that an example of irradiating the semiconductor layer 118 with theflash lamp light 132 from above (from the side opposite to the basesubstrate side) is described in this embodiment; however, the presentinvention is not limited to this example. The semiconductor layer 118can also be irradiated from below (from the base substrate side). Inthis case, the semiconductor layer 118 is irradiated with the flash lamplight 132 which is transmitted through the base substrate 100 and thelike. Alternatively, the semiconductor layer 118 may be irradiated withthe flash lamp light 132 from both above and below. When thesemiconductor layer 118 is irradiated with the flash lamp light 132 fromabove and below, defect repair can be achieved further effectively. Notethat the semiconductor layer 118 has a predetermined surface unevenness(with an Ra (arithmetic mean roughness) of about 5 nm to 50 nm) due tothe ion irradiation step or the division step. Therefore, when thesemiconductor layer 118 is irradiated with the flash lamp light 132 fromabove, reflection at the surface of the semiconductor layer 118 can besuppressed due to an anti-reflection effect of the above-mentionedunevenness, and effective defect repair can be performed. Note that inorder to improve the efficiency of irradiation with the flash lamp light132, the ion irradiation step, the division step, or the like may beintentionally performed under conditions where surface unevenness isincreased.

The flash lamp light 132 is preferably light having a continuousspectrum in a visible light region (at least from 400 nm to 700 nm),that is, white light. With the use of flash lamp light as mentionedabove, the flash lamp light 132 can penetrate to a sufficient depth evenwhen the semiconductor layer 118 is thick. That is, defect repair can befavorably performed.

Note that the irradiation with the flash lamp light 132 is preferablyperformed in, but not limited to, a vacuum or a reduced-pressureatmosphere. In the case of irradiation with the flash lamp light 132,unlike in the case of irradiation with laser light, the semiconductorlayer 118 is not melted. Therefore, a problem of surface oxidation orthe like is not so serious as in the case of using laser light, and asufficiently favorable semiconductor layer can also be obtained in thecase of an atmosphere other than a vacuum or a reduced-pressureatmosphere. Also in this regard, it can be said that a method using theflash lamp light 132 has an advantage over a method using laser light.

Needless to say, the irradiation with the flash lamp light 132 may beperformed in the air atmosphere or other atmospheres. For example, theirradiation with the flash lamp light 132 can be performed in an inertatmosphere such as nitrogen or argon. In order to perform theirradiation with the flash lamp light 132 in an inert atmosphere, theirradiation with the flash lamp light 132 may be performed in anairtight chamber, and the atmosphere in this chamber may be controlled.

There is no particular limitation on a flash lamp that is a light sourceof the flash lamp light; for example, a xenon lamp, a halogen lamp, ahigh pressure UV lamp, an ultra high pressure UV lamp, or the like canbe used. In particular, it can be said that a xenon lamp (a xenon flashlamp) is extremely suitable for the present invention because it caneasily emit light repeatedly with high light intensity. Although FIG. 2Billustrates an example in which a plurality of flash lamps are disposedparallel and are each provided with a reflector plate, the dispositionand structure of flash lamps (and reflector plates) are not limited tothis example. For example, a plurality of flash lamps may be disposedparallel and one or more large-sized reflector plates may be thendisposed above (or below) the flash lamps so that the efficiency ofirradiation with flash lamp light can be improved. The number and sizeof flash lamps can also be appropriately set.

Note that the time of irradiation with the flash lamp light issufficiently shorter than that of normal lamp light. For example, thetime of irradiation with the flash lamp light (pulse width) is, forexample, 10 μs to 100 ms (preferably 100 μs to 10 ms), whereas the timeof irradiation with normal lamp light is approximately 0.5 s or longer.Due to this difference in irradiation time, an extremely favorablesemiconductor substrate can be obtained in one embodiment of thedisclosed invention as compared to the case of irradiation with lamplight.

FIGS. 14A and 14B schematically illustrate a difference in effectbetween the case of irradiation with normal lamp light and the case ofirradiation with flash lamp light. FIG. 14A illustrates the case ofirradiation with normal lamp light, and FIG. 14B illustrates the case ofirradiation with flash lamp light. In the drawings, thick solid arrowsindicate how heat generated from light is conducted.

As illustrated in FIG. 14A, in the case of irradiation with normal lamplight 134, the irradiation time is long and the quantity of heatgenerated is large; thus, most of the heat generated in thesemiconductor layer 118 is conducted to the base substrate 100 throughthe insulating layer 116. In this case, the base substrate 100 may bemelted by the influence of heat. Even if not melted, the base substrate100 may be deformed to a level that is unacceptable to the process, andmobile ions in the base substrate 100 may move to the semiconductorlayer 118.

On the other hand, as illustrated in FIG. 14B, in the case ofirradiation with the flash lamp light 132, the irradiation time is shortand the quantity of heat generated is small; thus, most of the heatgenerated in the semiconductor layer 118 is not conducted to the basesubstrate 100. By irradiation with flash lamp light in this manner, adefect resulting from heat conduction to the base substrate 100 can besuppressed. In this regard, there is a significant technical differencebetween normal lamp light irradiation and flash lamp light irradiation.

By irradiating the semiconductor layer 118 with the flash lamp light 132as described above, a semiconductor substrate 150 including asemiconductor layer 120 whose defects have been repaired can be obtained(see FIG. 2C). Note that the semiconductor layer 120 is in a state closeto a single crystal semiconductor because defects have been repaired.

Note that after the irradiation with the flash lamp light 132 isperformed as described above, surface planarization treatment orthinning treatment may be performed on the semiconductor layer.Accordingly, characteristics of a semiconductor element to bemanufactured can be further improved. Surface planarization or thinningof the semiconductor layer can be performed by employing, for example,etching treatment (etchback treatment) by one of dry etching and wetetching or etching treatment (etchback treatment) by both of these.Alternatively, laser light irradiation treatment may be employed unlessit causes a variation in characteristics.

Note that the surface planarization treatment or the thinning treatmentof the semiconductor layer is not necessarily performed after theirradiation with the flash lamp light 132. For example, planarizationtreatment or the like may be performed before the irradiation with theflash lamp light 132. In this case, unevenness and defects on thesurface of the semiconductor layer are removed to some extent; thus,defect repair with a flash lamp can be performed more effectively.Furthermore, the above treatment may be performed both before and afterthe irradiation with the flash lamp light 132. Moreover, the irradiationwith the flash lamp light 132 and the above treatment may be alternatelyrepeated. By employing the irradiation with flash lamp light incombination with the above treatment in this manner, the unevenness,defects, and the like of the surface of the semiconductor layer can bedrastically reduced.

In one embodiment of the disclosed invention, flash lamp light is usedto repair defects of a semiconductor layer without melting thesemiconductor layer. Accordingly, a whole area of the semiconductorlayer can be treated at a time. Thus, productivity can be drasticallyimproved as compared to the case of using laser light. In addition,since a semiconductor layer is not melted, a crystal grain boundary andthe like resulting from generation of a melted region and an unmeltedregion are not produced. Thus, in-plane variation of a semiconductorlayer can be reduced, and a semiconductor layer having favorable anduniform characteristics can be obtained. Furthermore, compared toheating in thermal equilibrium with a furnace or the like, treatment canbe efficiently performed in an extremely short time. That is, alarge-area substrate having favorable and uniform characteristics can beprovided extremely efficiently.

Note that a semiconductor layer having favorable characteristics can beformed without being melted because a semiconductor layer which isseparated from a single crystal semiconductor layer (asemi-single-crystal semiconductor layer) is used as the semiconductorlayer. A semiconductor layer which is separated from a single crystalsemiconductor substrate (a semi-single-crystal semiconductor layer) hasa basic structure similar to that of a single crystal semiconductorlayer and differs from a single crystal semiconductor layer simply bythe presence of a large number of defects. In other words, if defectscan be effectively repaired, extremely high characteristics like thoseof a single crystal semiconductor can also be obtained in the case ofusing a non-melt defect repair process.

The use of flash lamp light is very favorable for the purpose of thedefect reduction. Since the irradiation with flash lamp light in thepresent invention is performed under non-melt conditions, it can beconsidered that not only thermal effect but also optical effectcontributes to defect repair. In other words, it can be assumed thatdefect repair is achieved by local bond rearrangement due to absorptionof band-gap light. Note that in the case of melting a semiconductorlayer, such as in the case of irradiating a semiconductor layer withlaser light, it can be said that thermal bond rearrangement mainlyoccurs. Furthermore, in the case of using so-called RTA (rapid thermalannealing), thermal effect with radiant heat mainly contributes.

The time of irradiation with flash light lamp (pulse width) can be 10 μsor more (preferably 10 μs to 100 ms, more preferably 100 μs to 10 ms),and that can be said to be sufficient time for rearrangement ofdefective bonds. In addition, since light from a flash lamp is so-calledwhite light, it acts on various types of defects as compared to the caseof using laser light that is monochromatic light. That is, even if thereare a plurality of defects having different energy levels in asemiconductor layer, light can be effectively absorbed to cause bondrearrangement and to repair the defects. Furthermore, with the use ofso-called white light, defects can be repaired without much dependenceon thickness; thus, a favorable semiconductor layer can be obtainedregardless of its thickness.

In addition, since the time of irradiation with flash lamp light issufficiently shorter than that with normal lamp light, the quantity ofheat provided to a base substrate can be sufficiently reduced.Accordingly, defects resulting from melting of a base substrate or thelike can be sufficiently reduced. Note that the time of irradiation withnormal lamp light is 0.5 s or more.

Note that in a process which requires melting of a semiconductor layer,such as in the case of laser light irradiation, there is a problem inthat the range of optimal power densities is narrow. On the other hand,in one embodiment of the disclosed invention, melting of a semiconductorlayer is not needed; thus, the range of optimal power densities is broadand that is extremely advantageous in a manufacturing process of asemiconductor substrate.

Embodiment 2

In Embodiment 2, a variation of the method for manufacturing asemiconductor substrate in Embodiment 1 will be described. Specifically,the case of employing planarization treatment by etching will bedescribed with reference to FIGS. 3A to 3D and FIGS. 4A to 4D. Note thatmany parts of a manufacturing process of a semiconductor substratedescribed in this embodiment are the same as those in Embodiment 1.Thus, description of parts overlapping with those in Embodiment 1 willbe omitted below, and differences will be mainly described.

First, a method illustrated in FIGS. 3A to 3D is described.

First, in accordance with the method described in Embodiment 1 or thelike, a base substrate 100 and a substrate 140 are bonded together, andthen, the substrate 140 is divided into a single crystal semiconductorsubstrate 142, and an insulating layer 116 and a semiconductor layer118. Accordingly, a semiconductor substrate including the semiconductorlayer 118 over the base substrate 100 is formed (see FIG. 3A). Note thatEmbodiment 1 can be referred to for steps to the structure of FIG. 3A;thus, detailed description is omitted. Note that the above-mentionedsemiconductor substrate has a structure where the insulating layer 116and the semiconductor layer 118 are sequentially stacked over the basesubstrate 100.

Next, the semiconductor layer 118 is irradiated with flash lamp light132. More specifically, a whole area of the semiconductor layer 118 isirradiated with the flash lamp light 132 (see FIG. 3B). In that case,the light intensity of the flash lamp light is set such that thesemiconductor layer 118 is not melted (or such that the planarity of thesurface of the semiconductor layer is not changed). The time ofirradiation with the flash lamp light (pulse width) is 10 μs or more(preferably 10 μs to 100 ms, more preferably 100 μs to 10 ms). Duringthe irradiation with the flash lamp light 132, the temperature of thebase substrate 100 is preferably kept at 300° C. or higher (morepreferably 500° C. or higher). Accordingly, defect repair can beperformed effectively.

The flash lamp light 132 is preferably light having a continuousspectrum in a visible light region (at least from 400 nm to 700 nm),that is, white light. With the use of flash lamp light as mentionedabove, the flash lamp light 132 can penetrate to a sufficient depth evenwhen the semiconductor layer 118 is thick. That is, defect repair can befavorably performed.

Embodiment 1 can be referred to for other conditions for the irradiationwith the flash lamp light 132, which are omitted here.

By irradiating the semiconductor layer 118 with the flash lamp light 132as described above, a semiconductor substrate 150 including asemiconductor layer 120 whose defects have been repaired can be obtained(see FIG. 3C). Note that the semiconductor layer 120 is in a state closeto a single crystal semiconductor because defects have been repaired.

Next, planarization treatment is performed on the semiconductor layer120. Specifically, for example, etching treatment (etchback treatment)by one of dry etching and wet etching or etching treatment (etchbacktreatment) by both of these can be employed. As dry etching treatment,etching treatment using an etching gas, for example, a chloride gas suchas boron chloride, silicon chloride, or carbon tetrachloride, a fluoridegas such as sulfur fluoride or nitrogen fluoride, a chlorine gas, anoxygen gas, or the like can be employed. As wet etching treatment,etching treatment using an etching solution, for example, atetramethylammonium hydroxide (abbr.: TMAH) solution or the like can beemployed.

As described above, by performing flash lamp light irradiation incombination with etching treatment, a semiconductor substrate 152including a semiconductor layer 160 whose defects have been drasticallyreduced and surface unevenness has been sufficiently reduced can beobtained (see FIG. 3D).

Next, a method illustrated in FIGS. 4A to 4D is described.

First, by a method similar to that described above, a semiconductorsubstrate including a semiconductor layer 118 over a base substrate 100is formed (see FIG. 4A). The semiconductor substrate has a structurewhere an insulating layer 116 and the semiconductor layer 118 aresequentially stacked over the base substrate 100.

Next, planarization treatment is performed on the semiconductor layer118. Specifically, for example, etching treatment (etchback treatment)by one of dry etching and wet etching or etching treatment (etchbacktreatment) by both of these can be employed. As dry etching treatment,etching treatment using an etching gas, for example, a chloride gas suchas boron chloride, silicon chloride, or carbon tetrachloride, a fluoridegas such as sulfur fluoride or nitrogen fluoride, a chlorine gas, anoxygen gas, or the like can be employed. As wet etching treatment,etching treatment using an etching solution, for example, atetramethylammonium hydroxide (abbr.: TMAH) solution or the like can beemployed.

By performing etching treatment on the semiconductor layer 118 in thismanner, a semiconductor layer 126 whose surface unevenness has beensufficiently reduced can be obtained (see FIG. 4B).

Next, the semiconductor layer 126 which has been planarized by etchingtreatment is irradiated with flash lamp light 132 (see FIG. 4C). In thatcase, the light intensity of the flash lamp light is set such that thesemiconductor layer 126 is not melted (or such that the planarity of thesurface of the semiconductor layer is not changed). The time ofirradiation with the flash lamp light (pulse width) is 10 μs or more(preferably 10 μs to 100 ms, more preferably 100 μs to 10 ms). Duringthe irradiation with the flash lamp light 132, the temperature of thebase substrate 100 is preferably kept at 300° C. or higher (morepreferably 500° C. or higher). Accordingly, defect repair can beperformed effectively.

The flash lamp light 132 is preferably light having a continuousspectrum in a visible light region (at least from 400 nm to 700 nm),that is, white light. With the use of flash lamp light as mentionedabove, the flash lamp light 132 can penetrate to a sufficient depth evenwhen the semiconductor layer 126 is thick. That is, defect repair can befavorably performed.

Embodiment 1 can be referred to for other conditions for the irradiationwith the flash lamp light 132, which are omitted here.

By irradiating the semiconductor layer 126 with the flash lamp light 132as described above, a semiconductor substrate 152 including asemiconductor layer 160 whose defects have been repaired can be obtained(see FIG. 4D). Note that in the method illustrated in FIGS. 4A to 4D,the irradiation with the flash lamp light 132 is performed after theetching treatment is performed. Accordingly, unevenness and defects ofthe surface of the semiconductor layer can be reduced to some extent;thus, defect repair with a flash lamp can be performed more effectively.Here, the semiconductor layer 160 is in a state close to a singlecrystal semiconductor because defects have been repaired.

This embodiment can be implemented in combination with Embodiment 1 asappropriate.

Embodiment 3

In Embodiment 3, another example of a method for manufacturing asemiconductor substrate of the present invention will be described withreference to FIGS. 5A to 5E and FIGS. 6A to 6C. Note that many parts ofa manufacturing process of a semiconductor substrate described in thisembodiment are the same as those in Embodiment 1. Thus, differences willbe mainly described.

First, a base substrate 100 is prepared (see FIG. 5A). Embodiment 1 canbe referred to for the details of the base substrate 100. In addition, asingle crystal semiconductor substrate 110 is prepared. Embodiment 1 canbe referred to also for the details of the single crystal semiconductorsubstrate 110.

Next, a variety of treatments are performed on the single crystalsemiconductor substrate 110 to form a damaged region 114 and aninsulating layer 116 (see FIG. 5B). Embodiment 1 may be referred to forthe details of the variety of treatments. Note that the damaged region114 is a region which contains ions at high concentration, and thesingle crystal semiconductor substrate 110 can be divided along theregion. Thus, the thickness of a semiconductor layer which is separatedfrom the single crystal semiconductor substrate 110 is determined by thedepth at which the damaged region 114 is formed. In this embodiment, thedamaged region 114 is formed at a depth of 50 nm to 300 nm from asurface of the single crystal semiconductor substrate 110. In addition,a structure where the single crystal semiconductor substrate 110 isprovided with the damaged region 114 and the insulating layer 116 isreferred to as a substrate 140.

After that, the base substrate 100 and the substrate 140 are bonded toeach other (see FIG. 5C). Then, heat treatment is performed on the basesubstrate 100 and the substrate 140 which have been bonded to eachother, to strengthen the bond. For the details, Embodiment 1 can bereferred to.

Next, the substrate 140 is divided along the damaged region 114 into asingle crystal semiconductor substrate 142 and a semiconductor layer 118(see FIG. 5D). Division of the substrate 140 is conducted by heattreatment. For the details, Embodiment 1 can be referred to.

Defects due to the ion irradiation step or the division step exist inthe semiconductor layer 118 formed as described above. If thesemiconductor layer 118 has many defects, characteristics as a singlecrystal semiconductor cannot be exhibited. Therefore, defect reductiontreatment is performed on the semiconductor layer 118.

In this embodiment, defect reduction in the semiconductor layer 118 isachieved by irradiating the semiconductor layer 118 with flash lamplight 132. More specifically, a whole area of the semiconductor layer118 is irradiated with the flash lamp light 132 (see FIG. 5E). In thatcase, the light intensity of the flash lamp light is set such that thesemiconductor layer 118 is not melted (or such that the planarity of thesurface of the semiconductor layer is not changed). Note that theoptimal light intensity of the flash lamp light varies depending on thethickness of the semiconductor layer 118 or the like; thus, the lightintensity of the flash lamp light is preferably set as appropriate. Thetime of irradiation with the flash lamp light (pulse width) is 10 μs ormore (preferably 10 μs to 100 ms, more preferably 100 μs to 10 ms).During the irradiation with the flash lamp light 132, the temperature ofthe base substrate 100 is preferably kept at 300° C. or higher (morepreferably 500° C. or higher). Accordingly, defect repair can beperformed effectively.

The flash lamp light 132 is preferably light having a continuousspectrum in a visible light region (at least from 400 nm to 700 nm),that is, white light. With the use of flash lamp light as mentionedabove, the flash lamp light 132 can penetrate to a sufficient depth evenwhen the semiconductor layer 118 is thick. That is, defect repair can befavorably performed.

Note that the irradiation with the flash lamp light 132 is preferablyperformed in, but not limited to, a vacuum or a reduced-pressureatmosphere. In the case of irradiation with the flash lamp light 132,unlike in the case of irradiation with laser light, the semiconductorlayer 118 is not melted. Therefore, a problem of surface oxidation orthe like is not so serious as in the case of using laser light, and asufficiently favorable semiconductor layer can also be obtained in thecase of an atmosphere other than a vacuum or a reduced-pressureatmosphere. Also in this regard, it can be said that a method using theflash lamp light 132 has an advantage over a method using laser light.

Needless to say, the irradiation with the flash lamp light 132 may beperformed in the air atmosphere or other atmospheres. For example, theirradiation with the flash lamp light 132 can be performed in an inertatmosphere such as nitrogen or argon. In order to perform theirradiation with the flash lamp light 132 in an inert atmosphere, theirradiation with the flash lamp light 132 may be performed in anairtight chamber, and the atmosphere in this chamber may be controlled.

There is no particular limitation on a flash lamp that is a light sourceof the flash lamp light; for example, a xenon lamp, a halogen lamp, ahigh pressure UV lamp, an ultra high pressure UV lamp, or the like canbe used. In particular, it can be said that a xenon lamp (a xenon flashlamp) is extremely suitable for the present invention because it caneasily emit light repeatedly with high light intensity. Although FIG. 5Eillustrates an example in which a plurality of flash lamps are disposedparallel and are each provided with a reflector plate, the dispositionand structure of flash lamps (and reflector plates) are not limited tothis example. The number and size of flash lamps can also beappropriately set.

By irradiating the semiconductor layer 118 with the flash lamp light 132as described above, a semiconductor substrate including a semiconductorlayer 120 whose defects have been repaired can be obtained. Note thatthe semiconductor layer 120 is in a state close to a single crystalsemiconductor because defects have been repaired.

Note that after the irradiation with the flash lamp light 132 isperformed as described above, surface planarization treatment or thelike may be performed. Accordingly, characteristics of a semiconductorelement to be manufactured can be further improved. Surfaceplanarization or the like can be performed by employing, for example,etching treatment (etchback treatment) by one of dry etching and wetetching or etching treatment (etchback treatment) by both of these.Alternatively, laser light irradiation treatment may be employed unlessit causes a variation in characteristics.

Next, a semiconductor layer 122A is formed by epitaxial growth(vapor-phase growth, vapor-phase epitaxial growth) on the semiconductorlayer 120 (see FIG. 6A). That is, the semiconductor layer 122A is asemiconductor layer which is influenced by the crystallinity of thesemiconductor layer 120. Here, the semiconductor layer 122A may beformed by selecting a material in accordance with the semiconductorlayer 120. In the case of forming a silicon layer as the semiconductorlayer 122A, the silicon layer can be formed by a plasma CVD method usinga mixed gas of a silane based gas (typically, silane) and a hydrogen gasas a source gas. The semiconductor layer 122A is formed to have athickness of approximately 5 nm to 500 nm, preferably approximately 10nm to 100 nm.

The above-mentioned source gas is a mixed gas in which the flow rate ofthe hydrogen gas is 50 times or more (preferably, 100 times or more) ashigh as that of the silane based gas. For example, silane (SiH₄) andhydrogen may be used after being mixed at flow rates of 4 sccm and 400sccm, respectively. By increasing the flow rate of the hydrogen gas, asemiconductor layer having high crystallinity can be formed. Thus, theamount of hydrogen contained in the semiconductor layer can be reduced.

Note that the silane based gas is not limited to the above-mentionedsilane, and disilane (Si₂H₆) or the like may be used. In addition, anoble gas may be added to the source gas.

Other conditions for formation of the semiconductor layer 122A by aplasma CVD method are as fallows: the frequency is 10 MHz to 200 MHz;the power, 5 W to 50 W; the pressure in the chamber, 10 Pa to 10³ Pa;the electrode interval (in the case of a parallel-plate type), 15 mm to30 mm; the temperature of the base substrate 100, 200° C. to 400° C. Thetypical conditions of the above are as follows: the frequency, 60 MHz;the power, 15 W; the pressure in the chamber, 100 Pa; the electrodeinterval, 20 mm; and the temperature of the base substrate 100, 280° C.The above film formation conditions are merely an example, and oneembodiment of the disclosed invention should not be construed as beinglimited to this example. The important point here is to form asemiconductor layer having high crystallinity (or a semiconductor layerhaving low hydrogen concentration or a semiconductor layer having lowhydrogen content) as the semiconductor layer 122A; therefore, thesemiconductor layer 122A may be formed by any formation method as longas that object can be achieved.

Note that a native oxide layer formed on a surface of the semiconductorlayer 120 and the like are preferably removed before the semiconductorlayer 122A is formed by epitaxial growth. This is because when an oxidelayer is formed on the surface of the semiconductor layer 120, theepitaxial growth which is influenced by the crystallinity of thesemiconductor layer 120 cannot be advanced and the crystallinity of thesemiconductor layer 122A is lowered. Here, the oxide layer can beremoved using a chemical solution containing a fluorinated acid, or thelike.

Next, a semiconductor layer 122B is formed over the semiconductor layer122A (see FIG. 6B). Here, the semiconductor layer 122B is formed byselecting a material in accordance with the semiconductor layer 122A. Inaddition, the semiconductor layer 122B is formed to have a thickness of200 nm to 2 μm (preferably, 400 nm to 1 μm). At that time, an oxidelayer formed on a surface of the semiconductor layer 122A is preferablyremoved.

The semiconductor layer 122B is formed to be a semiconductor layerhaving lower crystallinity than the semiconductor layer 122A.Alternatively, the semiconductor layer 122B is formed to be asemiconductor layer having higher hydrogen concentration (asemiconductor layer having higher hydrogen content) than thesemiconductor layer 122A. As such a semiconductor layer 122B, forexample, an amorphous semiconductor layer may be formed.

The formation method of the semiconductor layer 122B can be determinedas appropriate; however, the semiconductor layer 122B is preferablyformed at higher film-formation rate than at least the semiconductorlayer 122A. For example, when the semiconductor layer 122B is formed bya plasma CVD method using a mixed gas of a silane based gas (typically,silane) and a hydrogen gas as a source gas, it is preferable that theflow ratio of the hydrogen gas to the silane based gas be 2:1 to 20:1(preferably, 5:1 to 15:1). Further, it is preferable that the frequencybe set at 10 MHz to 200 MHz; the power, 5 W to 50 W; the pressure in thechamber, 10 Pa to 10³ Pa; the electrode interval (in the case of aparallel-plate type), 15 mm to 30 mm; the temperature of the basesubstrate 100, 200° C. to 400° C. Typically, the flow rates of silane(SiH₄) and hydrogen are 25 sccm and 150 sccm, respectively; thefrequency, 27 MHz; the power, 30 W, the pressure, 66.6 Pa; the electrodeinterval, 25 mm; and the substrate temperature, 280° C. Theabove-mentioned film-formation conditions are merely an example, and oneembodiment of the disclosed invention should not be construed as beinglimited to this example.

After that, heat treatment is performed and a semiconductor layer 124 isformed by solid-phase epitaxial growth (solid-phase growth) (see FIG.6C). Note that the semiconductor layer 122A corresponds to a lower layerregion 124A of the semiconductor layer 124, and the semiconductor layer122B corresponds to an upper layer region 124B of the semiconductorlayer 124.

The above-mentioned heat treatment can be performed using a heattreatment apparatus such as a rapid thermal annealing (RTA) apparatus, afurnace, a millimeter wave heating apparatus, or the like. As a heatingmethod of the heat treatment apparatus, a resistance heating method, alamp heating method, a gas heating method, an electromagnetic heatingmethod, or the like can be given. The heat treatment may be performed bylaser light irradiation or thermal plasma jet irradiation.

In general, a furnace is an external heating method, and the inside ofthe chamber and a process object are in thermal equilibrium. On theother hand, an RTA apparatus is an apparatus for performinginstantaneous heating (rapid heating) by directly giving energy to aprocess object, and the inside of the chamber and the process object arein thermal nonequilibrium. As the RTA apparatus, an RTA apparatus by alamp heating method (a lamp rapid thermal annealing (LRTA) apparatus),an RTA apparatus by a gas heating method using a heated gas (a gas rapidthermal annealing (GRTA) apparatus), an RTA apparatus by both a lampheating method and a gas heating method, or the like can be given.

When an RTA apparatus is used, it is preferable that the treatingtemperature be 500° C. to 750° C. and the treating time be 0.5 minutesto 10 minutes. When a furnace is used, it is preferable that thetreating temperature be 500° C. to 650° C. and the treating time be 1hour to 4 hours. Needless to say, there is no need to interpret treatingtemperature and treating time as being limited to those given above, andit is possible to set treating temperature and treating time asappropriate depending on the allowable temperature limit of the basesubstrate and the like.

Through the above steps, a stacked structure of the semiconductor layer120 and the semiconductor layer 124 is formed. Note that if asemiconductor layer having high crystallinity is not necessary, theabove-mentioned heat treatment step can be omitted. Furthermore, insteadof the above-mentioned heat treatment, flash lamp light irradiation maybe performed under non-melt conditions.

In this embodiment, after the semiconductor layer 122A (a semiconductorlayer having high crystallinity, a semiconductor layer having lowhydrogen concentration) is formed by vapor-phase growth, thesemiconductor layer 122B (a semiconductor layer having lowcrystallinity, a semiconductor layer having high hydrogen concentration)is formed thick, and then, the semiconductor layer 124 is formed bysolid-phase growth. Thus, the film formation rate is secured and theoccurrence of separation between semiconductor layers can be suppressed.That is, a single crystal semiconductor layer which has a predeterminedthickness can be formed with high productivity and high yield.

It can be considered that the reason why the occurrence of separationcan be reduced by forming the stacked structure of the semiconductorlayer 122A having high crystallinity and the semiconductor layer 122Bhaving low crystallinity over the semiconductor layer 120 and performingsolid-phase growth as described above is because the difference incrystallinity between adjacent layers becomes smaller, so that bondingbetween atoms at the interface is strengthened and adhesion isincreased.

In this embodiment, although the semiconductor layer 122A having highcrystallinity is formed between the semiconductor layer 120 and thesemiconductor layer 122B having low crystallinity, there is no need tointerpret one embodiment of the disclosed invention as being limitedthereto in consideration of the above reason. That is, a plurality ofsemiconductor layers having different crystallinities may be providedbetween the semiconductor layer 120 and the semiconductor layer 122Bhaving low crystallinity. For example, a semiconductor layer having highcrystallinity, a semiconductor layer having slightly high crystallinity,and a semiconductor layer having low crystallinity can be sequentiallyformed over a semiconductor layer (in this embodiment, the semiconductorlayer 120). With this structure, adhesion can be further improved.

In terms of adhesion at the interface, the stacked structure ispreferably formed so as to be exposed to as little air or the like aspossible. For example, the semiconductor layer 122A and thesemiconductor layer 122B are preferably formed successively in the samechamber.

In the manner described above, a semiconductor substrate having a thicksemiconductor layer can be manufactured. Note that in this embodiment,planarization treatment is not performed on the surface of thesemiconductor layer 120; thus, the surface of the semiconductor layer124 is strongly influenced by the surface of the semiconductor layer120. Therefore, if necessary, the surface of the semiconductor layer 124may be planarized.

In this embodiment, the method in which the semiconductor layer 120 andthe semiconductor layer 124 are formed over the base substrate 100 withthe insulating layer 116 interposed therebetween is described. However,the present invention should not be interpreted as being limitedthereto. For example, layers having various functions (hereinafterreferred to as functional layers) may be provided below thesemiconductor layer 120. For example, a layer containing a conductivematerial, a layer containing an impurity element (a semiconductor layercontaining an impurity element), or the like may be formed as afunctional layer.

Note that in this embodiment, the semiconductor layer 122A and thesemiconductor layer 122B are formed after the semiconductor layer 120whose defects have been reduced by irradiation with the flash lamp light132 is formed. However, the present invention should not be interpretedas being limited thereto. For example, it is also possible to form thesemiconductor layer 122A and the semiconductor layer 122B over thesemiconductor layer 118 and then perform irradiation with the flash lamplight 132. In this case, defects in the semiconductor layer 118 can alsobe reduced sufficiently.

This embodiment can be implemented in combination with Embodiment 1 or 2as appropriate.

Embodiment 4

In Embodiment 4, an example of irradiation with flash lamp light will bedescribed with reference to FIGS. 7A and 7B. Note that a methoddescribed in this embodiment is merely an example, and one embodiment ofthe disclosed invention should not be interpreted as being limited tothe method described in this embodiment.

First, a case in which a region irradiated with flash lamp light 132 inthe semiconductor layer 200 is large is described (see FIG. 7A). In thiscase, a whole area of the semiconductor layer 200 is irradiated with theflash lamp light 132. By irradiating the whole area of the semiconductorlayer 200 with flash lamp light as described above, the time forirradiation with flash lamp light can be suppressed to a minimum. Thatis, a semiconductor substrate can be manufactured efficiently.

Next, a case in which a region irradiated with the flash lamp light 132in the semiconductor layer 200 is small is described (see FIG. 7B). Notethat FIG. 7B illustrates an example in which the semiconductor layer 200is divided into four regions, which are separately irradiated with theflash lamp light 132. Flash lamp light irradiation regions (A to D) areprovided to overlap partly so that the whole area of the semiconductorlayer 200 be irradiated with flash lamp light.

In the present invention, the irradiation with the flash lamp light 132is performed under non-melt conditions. Thus, characteristic variationof a single crystal semiconductor layer, which is a problem caused inthe case of laser light irradiation, is not caused. More specifically,there is little difference in characteristics between a portion whereflash lamp light irradiation regions overlap and a portion where flashlamp light irradiation regions do not overlap.

In this manner, even if regions irradiated with the flash lamp light 132overlap, the difference in characteristics can be sufficiently small.Thus, a semiconductor substrate having an extremely uniformsemiconductor layer can be provided. The effect of the present inventionis significant, particularly on a large-area substrate where irradiationregions overlap.

This embodiment can be implemented in combination with any ofEmbodiments 1 to 3 as appropriate.

Embodiment 5

In Embodiment 5, a method for manufacturing a semiconductor device usingthe above-described semiconductor substrate will be described withreference to FIGS. 8A to 8D, FIGS. 9A to 9D, and FIGS. 10A and 10B.Here, a method for manufacturing a semiconductor device including aplurality of transistors as an example of the semiconductor device isdescribed. Note that various semiconductor devices can be formed withthe use of transistors described below in combination.

First, a semiconductor substrate manufactured by the method described inEmbodiment 2 is prepared (see FIG. 8A). Note that in this embodiment, amethod for manufacturing a semiconductor device using a semiconductorsubstrate manufactured by the method described in Embodiment 2 isdescribed; however, one embodiment of the disclosed invention is notlimited thereto. A semiconductor substrate manufactured by the methoddescribed in Embodiment 1 or the like may be used.

In order to control the threshold voltages of TFTs, a p-type impurityelement such as boron, aluminum, or gallium or an n-type impurityelement such as phosphorus or arsenic may be added to a semiconductorlayer 1000 (corresponding to the semiconductor layer 160 in Embodiment2). A region to which the impurity element is added and the kind ofimpurity element to be added can be changed as appropriate. For example,a p-type impurity element can be added to a formation region of ann-channel TFT, and an n-type impurity element can be added to aformation region of a p-channel TFT. The above impurity element may beadded at a dose of approximately 1×10¹⁵/cm² to 1×10¹⁷/cm². Then, thesemiconductor layer 1000 is divided into an island shape to form asemiconductor layer 1002 and a semiconductor layer 1004 (see FIG. 8B).

Next, a gate insulating layer 1006 is formed to cover the semiconductorlayer 1002 and the semiconductor layer 1004 (see FIG. 8C). Here, asingle-layer silicon oxide film is formed by a plasma CVD method.Alternatively, a film containing silicon oxynitride, silicon nitrideoxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide,or the like may be formed to have a single-layer structure or a stackedstructure as the gate insulating layer 1006.

As a manufacturing method other than a plasma CVD method, a sputteringmethod or a method using oxidation or nitridation by high density plasmatreatment can be given. High-density plasma treatment is performedusing, for example, a mixed gas of a noble gas such as helium, argon,krypton, or xenon and a gas such as oxygen, nitrogen oxide, ammonia,nitrogen, or hydrogen. In this case, if plasma excitation is performedby introduction of microwaves, plasma with low electron temperature andhigh density can be generated. The surfaces of the semiconductor layersare oxidized or nitrided with oxygen radicals (OH radicals may beincluded) or nitrogen radicals (NH radicals may be included) which aregenerated by such high-density plasma, whereby the insulating layer isformed to a thickness of 1 nm to 20 nm, preferably 2 nm to 10 nm to bein contact with the semiconductor layers.

Since the oxidation or nitridation of the semiconductor layers by theabove-described high-density plasma treatment is a solid-phase reaction,the interface state density between the gate insulating layer 1006 andeach of the semiconductor layer 1002 and the semiconductor layer 1004can be drastically reduced. Further, when the semiconductor layers aredirectly oxidized or nitrided by the high-density plasma treatment,variation in the thickness of the insulating layer to be formed can besuppressed. Since the semiconductor layers have crystallinity, even whenthe surfaces of the semiconductor layers are oxidized by a solid-phasereaction by using the high-density plasma treatment, nonuniformoxidation at a crystal grain boundary can be suppressed; thus, a gateinsulating layer with favorable uniformity and low interface statedensity can be formed. When an insulating layer formed by high-densityplasma treatment as described above is used for a part or whole of thegate insulating layer of a transistor, variation in characteristics canbe suppressed.

Alternatively, the gate insulating layer 1006 can be formed by thermallyoxidizing the semiconductor layer 1002 and the semiconductor layer 1004.In the case of using such thermal oxidation, a base substrate with highheat resistance is preferably used.

Note that after a gate insulating layer 1006 containing hydrogen isformed, hydrogen contained in the gate insulating layer 1006 may bedispersed into the semiconductor layer 1002 and the semiconductor layer1004 by performing heat treatment at a temperature of 350° C. to 450° C.In this case, the gate insulating layer 1006 may be formed by depositingsilicon nitride or silicon nitride oxide by a plasma CVD method.Further, the process temperature after formation of the gate insulatinglayer 1006 and before hydrogen diffusion treatment is preferably set to350° C. or lower. If hydrogen is supplied to the semiconductor layer1002 and the semiconductor layer 1004 in this manner, defects in thesemiconductor layer 1002, in the semiconductor layer 1004, at theinterface between the gate insulating layer 1006 and the semiconductorlayer 1002, and at the interface between the gate insulating layer 1006and the semiconductor layer 1004 can be effectively reduced.

Next, a conductive layer is formed over the gate insulating layer 1006,and then, the conductive layer is processed (patterned) into apredetermined shape, whereby electrodes 1008 are formed over thesemiconductor layers 1002 and 1004 (see FIG. 8D). The conductive layercan be formed by a CVD method, a sputtering method, or the like. Theconductive layer can be formed using a material such as tantalum (Ta),tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper(Cu), chromium (Cr), or niobium (Nb). Alternatively, an alloy materialcontaining the above-mentioned metal as a main component or a compoundcontaining the above-mentioned metal can also be used. Furtheralternatively, a semiconductor material, such as polycrystalline siliconwhich is obtained by doping a semiconductor with an impurity elementthat imparts a conductivity type, may be used.

Although the electrodes 1008 are formed using a single-layer conductivelayer in this embodiment, a semiconductor device of one embodiment ofthe disclosed invention is not limited to the structure. Each of theelectrodes 1008 may be formed of plural conductive layers which arestacked. In the case of a two-layer structure, for example, a molybdenumfilm, a titanium film, a titanium nitride film, or the like may be usedas the lower layer, and an aluminum film or the like may be used as theupper layer. In the case of a three-layer structure, a stacked structureof a molybdenum film, an aluminum film, and a molybdenum film, a stackedstructure of a titanium film, an aluminum film, and a titanium film, orthe like may be used.

Note that a mask used for forming the electrodes 1008 may be formedusing a material such as silicon oxide or silicon nitride oxide. In thiscase, a step of forming a mask by patterning a silicon oxide film, asilicon nitride oxide film, or the like is additionally needed; however,the amount of decrease in film thickness of the mask in etching issmaller than that in the case of using a resist material; thus, theelectrodes 1008 with a more precise shape can be formed. Alternatively,the electrodes 1008 may be selectively formed by a droplet dischargemethod without using a mask. Here, a droplet discharge method refers toa method in which droplets containing a predetermined composition aredischarged or ejected to form a predetermined pattern, and includes anink-jet method and the like in its category.

Alternatively, the electrodes 1008 can be formed by etching theconductive layer to have a desired tapered shape by an inductivelycoupled plasma (ICP) etching method with appropriate adjustment ofetching conditions (e.g., the amount of electric power applied to acoiled electrode layer, the amount of electric power applied to asubstrate-side electrode layer, the temperature of the substrate-sideelectrode layer, and the like). The tapered shape can be adjustedaccording to the shape of the mask. Note that as an etching gas, achlorine based gas such as chlorine, boron chloride, silicon chloride,or carbon tetrachloride, a fluorine based gas such as carbontetrafluoride, sulfur fluoride, or nitrogen fluoride, oxygen, or thelike can be used as appropriate.

Next, an impurity element imparting one conductivity type is added tothe semiconductor layer 1002 and the semiconductor layer 1004 using theelectrodes 1008 as masks (see FIG. 9A). In this embodiment, an impurityelement imparting n-type conductivity (e.g., phosphorus or arsenic) isadded to the semiconductor layer 1002, and an impurity element impartingp-type conductivity (e.g., boron) is added to the semiconductor layer1004. Note that when the impurity element imparting n-type conductivityis added to the semiconductor layer 1002, the semiconductor layer 1004to which the p-type impurity element is added is covered with a mask orthe like so that the impurity element imparting n-type conductivity isadded selectively. When the impurity element imparting p-typeconductivity is added to the semiconductor layer 1004, the semiconductorlayer 1002 to which the impurity element imparting n-type conductivityis added is covered with a mask or the like so that the impurity elementimparting p-type conductivity is added selectively. Alternatively, afteran impurity element imparting one of p-type and n-type conductivities isadded to the semiconductor layers 1002 and 1004, an impurity elementimparting the other conductivity type may be added to only one of thesemiconductor layers at a higher concentration. By the addition of theimpurity elements, impurity regions 1010 and impurity regions 1012 areformed in the semiconductor layer 1002 and the semiconductor layer 1004,respectively.

Next, sidewalls 1014 are formed on side surfaces of the electrodes 1008(see FIG. 9B). The sidewalls 1014 can be formed by, for example, newlyforming an insulating layer to cover the gate insulating layer 1006 andthe electrodes 1008 and by partially etching the newly formed insulatinglayer by anisotropic etching mainly in a perpendicular direction. Notethat the gate insulating layer 1006 may also be etched partially by theanisotropic etching described above. For the insulating layer forforming the sidewalls 1014, a film containing silicon, silicon oxide,silicon nitride, silicon oxynitride, silicon nitride oxide, an organicmaterial, or the like may be formed to have a single layer structure ora stacked structure by a plasma CVD method, a sputtering method, or thelike. In this embodiment, a 100-nm-thick silicon oxide film is formed bya plasma CVD method. In addition, as an etching gas, a mixed gas of CHF₃and helium can be used. Note that the steps of forming the sidewalls1014 are not limited to the steps described here.

Next, impurity elements each imparting one conductivity type are addedto the semiconductor layer 1002 and the semiconductor layer 1004 usingthe gate insulating layer 1006, the electrodes 1008, and the sidewalls1014 as masks (see FIG. 9C). Note that the impurity elements impartingthe same conductivity types as the impurity elements which have beenadded to the semiconductor layer 1002 and the semiconductor layer 1004in the previous step are added to the semiconductor layer 1002 and thesemiconductor layer 1004 at higher concentrations. Note that when theimpurity element imparting n-type conductivity is added to thesemiconductor layer 1002, the semiconductor layer 1004 to which thep-type impurity element is added is covered with a mask or the like sothat the impurity element imparting n-type conductivity is addedselectively. When the impurity element imparting p-type conductivity isadded to the semiconductor layer 1004, the semiconductor layer 1002 towhich the impurity element imparting n-type conductivity is added iscovered with a mask or the like so that the impurity element impartingp-type conductivity is added selectively.

By the addition of the impurity element, a pair of high-concentrationimpurity regions 1016, a pair of low-concentration impurity regions1018, and a channel formation region 1020 are formed in thesemiconductor layer 1002. In addition, by the addition of the impurityelement, a pair of high-concentration impurity regions 1022, a pair oflow-concentration impurity regions 1024, and a channel formation region1026 are formed in the semiconductor layer 1004. The high-concentrationimpurity regions 1016 and the high-concentration impurity regions 1022each function as a source or a drain, and the low-concentration impurityregions 1018 and the low-concentration impurity regions 1024 eachfunction as an LDD (lightly doped drain) region.

Note that the sidewalls 1014 formed over the semiconductor layer 1002and the sidewalls 1014 formed over the semiconductor layer 1004 may beformed so as to have the same length or different lengths in a directionin which carriers travel (in a direction parallel to a so-called channellength). The length of each of the sidewalls 1014 over the semiconductorlayer 1004 which constitutes part of a p-channel transistor ispreferably larger than the length of each of the sidewalls 1014 over thesemiconductor layer 1002 which constitutes part of an n-channeltransistor. This is because boron which is added for forming a sourceand a drain in the p-channel transistor is easily diffused and a shortchannel effect is easily induced. By increasing the lengths of thesidewalls 1014 in a carrier travelling direction of the p-channeltransistor, boron can be added to the source and the drain at highconcentration, whereby the resistance of the source and the drain can bereduced.

In order to further reduce the resistance of the source and the drain, asilicide layer may be formed by forming silicide in part of thesemiconductor layers 1002 and 1004. The silicide is formed by placing ametal in contact with the semiconductor layers and causing a reactionbetween the metal and silicon in the semiconductor layers by heattreatment (e.g., a GRTA method, an LRTA method, or the like). For thesilicide layer, cobalt silicide or nickel silicide may be used. In thecase where the semiconductor layers 1002 and 1004 are thin, silicidereaction may proceed to the bottoms of the semiconductor layers 1002 and1004. As a metal material used for the siliciding, the following can beused: titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt(Co), zirconium (Zr), hafnium (Hf), tantalum (Ta), vanadium (V),neodymium (Nd), chromium (Cr), platinum (Pt), palladium (Pd), or thelike. Further, a silicide layer can also be formed by laser lightirradiation or the like.

Through the aforementioned steps, an n-channel transistor 1028 and ap-channel transistor 1030 are formed. Note that although conductivelayers each serving as a source electrode or a drain electrode have notbeen formed at the stage shown in FIG. 9C, a structure including theseconductive layers each serving as a source electrode or a drainelectrode may also be referred to as a transistor.

Next, an insulating layer 1032 is formed to cover the n-channeltransistor 1028 and the p-channel transistor 1030 (see FIG. 9D). Theinsulating layer 1032 is not always necessary; however, the formation ofthe insulating layer 1032 can prevent impurities such as an alkali metaland an alkaline earth metal from penetrating the n-channel transistor1028 and the p-channel transistor 1030. Specifically, the insulatinglayer 1032 is preferably formed using a material such as silicon oxide,silicon nitride, silicon oxynitride, silicon nitride oxide, aluminumnitride, aluminum oxide, or the like. In this embodiment, a siliconnitride oxide film with a thickness of approximately 600 nm is used asthe insulating layer 1032. In this case, the above-describedhydrogenation step may be performed after the silicon nitride oxide filmis formed. Note that although the insulating layer 1032 is formed tohave a single-layer structure in this embodiment, it is needless to saythat the insulating layer 1032 may have a stacked structure. Forexample, in the case of a two-layer structure, the insulating layer 1032may have a stacked structure of a silicon oxynitride film and a siliconnitride oxide film.

Next, an insulating layer 1034 is formed over the insulating layer 1032to cover the n-channel transistor 1028 and the p-channel transistor1030. The insulating layer 1034 may be formed using an organic materialhaving heat resistance, such as polyimide, acrylic, benzocyclobutene,polyamide, or epoxy. Other than such an organic material, it is alsopossible to use a low-dielectric constant material (a low-k material), asiloxane based resin, silicon oxide, silicon nitride, siliconoxynitride, silicon nitride oxide, phosphosilicate glass (PSG),borophosphosilicate glass (BPSG), alumina, or the like. Here, thesiloxane based resin corresponds to a resin including a Si—O—Si bondwhich is formed using a siloxane based material as a starting material.The siloxane based resin may include, besides hydrogen, at least one offluorine, an alkyl group, and aromatic hydrocarbon as a substituent.Alternatively, the insulating layer 1034 may be formed by stackingplural insulating layers using any of these materials.

For the formation of the insulating layer 1034, the following method canbe employed depending on the material of the insulating layer 1034: aCVD method, a sputtering method, an SOG method, a spin coating method, adipping method, a spray coating method, a droplet discharge method(e.g., an ink-jet method, screen printing, offset printing, or thelike), a doctor knife, a roll coater, a curtain coater, a knife coater,or the like.

Next, contact holes are formed in the insulating layers 1032 and 1034 sothat each of the semiconductor layers 1002 and 1004 is partiallyexposed. Then, conductive layers 1036 and conductive layers 1038 areformed in contact with the semiconductor layer 1002 and thesemiconductor layer 1004, respectively, through the contact holes (seeFIG. 10A). The conductive layers 1036 and the conductive layers 1038serve as source electrodes and drain electrodes of the respectivetransistors. Note that in this embodiment, as an etching gas used forforming the contact holes, a mixed gas of CHF₃ and He is employed;however, the etching gas is not limited thereto.

The conductive layers 1036 and the conductive layers 1038 can be formedby a CVD method, a sputtering method, or the like. Specifically, theconductive layers 1036 and the conductive layers 1038 can be formedusing aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta),molybdenum (Mo), nickel (Ni), platinum (Pt), copper (Cu), gold (Au),silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si),or the like. Moreover, an alloy containing the above-mentioned materialas its main component or a compound containing the above-mentionedmaterial may be used. The conductive layers 1036 and the conductivelayers 1038 may each have a single-layer structure or a stackedstructure.

As examples of an alloy containing aluminum as its main component, analloy containing aluminum as its main component and also containingnickel, and an alloy containing aluminum as its main component and alsocontaining nickel and one or both of carbon and silicon can be given.Since aluminum and aluminum silicon (Al—Si) have low resistance and areinexpensive, aluminum and aluminum silicon are suitable as a materialfor forming the conductive layers 1036 and the conductive layers 1038.In particular, aluminum silicon is preferable because a hillock can beprevented from generating due to resist baking at the time ofpatterning. Further, a material in which Cu is mixed into aluminum atapproximately 0.5% may be used instead of silicon.

In the case where each of the conductive layers 1036 and the conductivelayers 1038 is formed to have a stacked structure, a stacked structureof a barrier film, an aluminum silicon film, and a barrier film, astacked structure of a barrier film, an aluminum silicon film, atitanium nitride film, and a barrier film, or the like may be employed,for example. Note that a barrier film refers to a film formed usingtitanium, a nitride of titanium, molybdenum, a nitride of molybdenum, orthe like. By forming the conductive layers such that an aluminum film oran aluminum silicon film is interposed between barrier films, generationof hillocks of aluminum or aluminum silicon can be further prevented.Moreover, by forming the barrier film using titanium that is a highlyreducible element, even if a thin oxide film is formed on thesemiconductor layers 1002 and 1004, the oxide film is reduced by thetitanium contained in the barrier film, whereby preferable contactbetween the conductive layers 1036 and the semiconductor layer 1002 andbetween the conductive layers 1038 and the semiconductor layer 1004 canbe obtained. Further, it is also possible to stack a plurality ofbarrier films. In that case, for example, each of the conductive layers1036 and the conductive layers 1038 can be formed to have a five-layerstructure of titanium, titanium nitride, aluminum silicon, titanium, andtitanium nitride in order from the bottom or a stacked structure of morethan five layers.

For the conductive layers 1036 and the conductive layers 1038, tungstensilicide formed by a chemical vapor deposition method using a WF₆ gasand a SiH₄ gas may be used. Alternatively, tungsten formed by hydrogenreduction of WF₆ may be used for the conductive layers 1036 and 1038.

Note that the conductive layers 1036 are connected to thehigh-concentration impurity regions 1016 of the n-channel transistor1028. The conductive layers 1038 are connected to the high-concentrationimpurity regions 1022 of the p-channel transistor 1030.

FIG. 10B is a plan view of the n-channel transistor 1028 and thep-channel transistor 1030 which are illustrated in FIG. 10A. Here, thecross section taken along the line M-N in FIG. 10B corresponds to thecross-sectional view of FIG. 10A. Note that in FIG. 10B, the conductivelayers 1036, the conductive layers 1038, the insulating layers 1032 and1034, and the like are omitted for simplicity.

Note that although the case where each of the n-channel transistor 1028and the p-channel transistor 1030 includes one electrode 1008 serving asa gate electrode is described in this embodiment as an example, oneembodiment of the disclosed invention is not limited to this structure.A transistor according to one embodiment of the disclosed invention mayhave, for example, a multi-gate structure in which a plurality ofelectrodes serving as gate electrodes are included and electricallyconnected to one another.

In this embodiment, a semiconductor substrate which has been subjectedto etching treatment and flash lamp light irradiation treatment is used.Accordingly, it is possible to manufacture, at low cost, a transistorwhich has a low subthreshold value and a high field-effect mobility andcan operate at high speed and can be driven at low voltage.

This embodiment can be implemented in combination with any ofEmbodiments 1 to 4 as appropriate.

EXAMPLE 1

Characteristics of a silicon layer which is formed over a glasssubstrate by the method according to one embodiment of the disclosedinvention were examined. Description is made below with reference toFIGS. 11A and 11B.

First, a silicon layer was formed over a glass substrate by the methoddescribed in the above embodiment. In this example, a silicon layerhaving a thickness of 120 nm was formed over a glass substrate having athickness of 0.7 mm, and the silicon layer was then irradiated withflash lamp light. Note that the temperature of the glass substrateduring flash lamp light irradiation was about 500° C.

The light intensity of the flash lamp light was varied in this sample,and Raman spectra were observed. More specifically, the dependence ofpeak of Raman spectrum (also called Raman peak) on flash lamp lightintensity (see FIG. 11A) and the dependence of full width at halfmaximum of Raman peak on flash lamp light intensity (see FIG. 11B) wereobserved. In FIG. 11A, the horizontal axis is lamp power (arbitraryunit) and the vertical axis is peak wavenumber (cm⁻¹) of Raman peak. InFIG. 11B, the horizontal axis is lamp power (arbitrary unit) and thevertical axis is full width at half maximum (cm⁻¹) of Raman peak. Here,the horizontal axis of FIG. 11A corresponds to the horizontal axis ofFIG. 11B.

In FIG. 11A, the mean value of Raman peak wavenumbers at a lamp power of9 is 519.5 cm⁻¹ to 519.6 cm⁻¹ and the value is close to that of singlecrystal silicon. Note that the Raman peak wavenumber of single crystalsilicon is about 520 cm⁻¹. A Raman spectrum is used to measure a shiftin wavenumber from incident light to scattered light (Raman scatteredlight), and the shift in wavenumber corresponds to vibrational energybetween atoms. Thus, the fact that the wavenumber of Raman peak iscloser to that of single crystal silicon means that the bonding state iscloser to that of single crystal silicon. That is, it can be said thatcharacteristics of a silicon layer become closer to those of singlecrystal silicon when the silicon layer is irradiated with flash lamplight at appropriate light intensity.

In FIG. 11B, the full width at half maximum of Raman spectrum is about 5cm⁻¹ or less at a lamp power of 9 or more. The fact that the full widthat half maximum is small means that many interatomic bonds are in thesame state. Thus, characteristics of a silicon layer become closer tothose of single crystal silicon when the silicon layer is irradiatedwith flash lamp light. On the other hand, a silicon layer which is notirradiated with flash lamp light has a large full width at half maximumand has a variation in interatomic bonding state. In other words, it canbe said that the silicon layer has lower crystallinity than singlecrystal silicon.

In summary, it can be seen that when a silicon layer is irradiated withflash lamp light at appropriate intensity, its Raman peak is at awavenumber of about 519.2 cm⁻¹ to 520 cm⁻¹ and a full width at halfmaximum of about 5 cm⁻¹ or less.

This example can be implemented in combination with any of Embodiments 1to 5 as appropriate.

EXAMPLE 2

It is confirmed that a semiconductor layer is not melted by irradiationwith flash lamp light that is one embodiment of the disclosed invention.Specifically, surface unevenness of a semiconductor layer was observedbefore and after irradiation with flash lamp light. Description is madebelow with reference to FIGS. 12A and 12B and FIGS. 13A and 13B. Notethat in this example, the same sample as that used in Example 1 wasused.

First, the condition of surface unevenness of a silicon layer beforeirradiation with flash lamp light was observed. Specifically, surfaceunevenness was observed with an atomic force microscope (AFM) in threerandomly selected regions (No. 01, No. 02, and No. 03) (see FIG. 12A).The surface unevenness was evaluated using Ra (arithmetic meanroughness), P-V (maximum height difference), and Rms (root-mean-squareroughness) (see FIG. 12B).

After that, the condition of surface roughness of the silicon layerafter irradiation with flash lamp light was observed. Specifically, fourrandomly selected regions (No. 04, No. 05, No. 06, and No. 07) wereobserved (see FIG. 13A). The surface roughness was evaluated using Ra(arithmetic mean roughness), P-V (maximum height difference), and Rms(root-mean-square roughness) (see FIG. 13B). Note that the intensity offlash lamp light with which the silicon layer was irradiated correspondsto the intensity at a lamp power of 9 in Example 1.

As can be seen from FIGS. 12B and 13B, there is no large difference ineach of Ra (arithmetic mean roughness), P-V (maximum height difference),and Rms (root-mean-square roughness) before and after irradiation withflash lamp light. On the other hand, it is known that a surface of asilicon layer which has been melted by irradiation with pulsed laserlight has an Ra of about 1 nm to 3 nm, a P-V of about 10 nm to 40 nm,and an Rms of about 1 nm to 5 nm.

From the above results, it can be confirmed that a semiconductor layeris not melted by irradiation with flash lamp light that is oneembodiment of the disclosed invention.

This example can be implemented in combination with any of Embodiments 1to 5 and Example 1 as appropriate.

This application is based on Japanese Patent Application serial no.2008-146914 filed with Japan Patent Office on Jun. 4, 2008, the entirecontents of which are hereby incorporated by reference.

1. A method for manufacturing a semiconductor substrate, comprising thesteps of: irradiating a surface of a single crystal semiconductorsubstrate with ions to form a damaged region in the single crystalsemiconductor substrate; forming an insulating layer over the surface ofthe single crystal semiconductor substrate; disposing a surface of asubstrate having an insulating surface and a surface of the insulatinglayer in contact with each other to bond the substrate having theinsulating surface and the single crystal semiconductor substrate toeach other; performing heat treatment to divide the single crystalsemiconductor substrate along the damaged region and to form asemiconductor layer over the substrate having the insulating surface;and irradiating a surface of the semiconductor layer with light from aflash lamp under a condition where the semiconductor layer is notmelted, to repair a defect.
 2. The method for manufacturing asemiconductor substrate according to claim 1, further comprising thestep of performing planarization treatment on the semiconductor layerbefore or after the irradiation with the light from the flash lamp. 3.The method for manufacturing a semiconductor substrate according toclaim 2, wherein the planarization treatment includes etching treatment.4. The method for manufacturing a semiconductor substrate according toclaim 1, wherein a time of irradiation with the light from the flashlamp is 10 μs or more.
 5. The method for manufacturing a semiconductorsubstrate according to claim 1, wherein the light from the flash lamphas a continuous spectrum in a wavelength range from 400 nm to 700 nm.6. The method for manufacturing a semiconductor substrate according toclaim 1, wherein the flash lamp is a xenon lamp.
 7. The method formanufacturing a semiconductor substrate according to claim 1, wherein atemperature of the substrate having the insulating surface is kept at300° C. or higher during the irradiation with the light from the flashlamp.
 8. A method for manufacturing a semiconductor substrate,comprising the steps of: irradiating a surface of a single crystalsemiconductor substrate with ions to form a damaged region in the singlecrystal semiconductor substrate; forming a first insulating layer overthe surface of the single crystal semiconductor substrate; forming asecond insulating layer over a surface of a substrate having aninsulating surface; disposing a surface of the second insulating layerand a surface of the first insulating layer in contact with each otherto bond the substrate having the insulating surface and the singlecrystal semiconductor substrate to each other; performing heat treatmentto divide the single crystal semiconductor substrate along the damagedregion and to form a semiconductor layer over the substrate having theinsulating surface; and irradiating a surface of the semiconductor layerwith light from a flash lamp under a condition where the semiconductorlayer is not melted, to repair a defect.
 9. The method for manufacturinga semiconductor substrate according to claim 8, further comprising thestep of performing planarization treatment on the semiconductor layerbefore or after the irradiation with the light from the flash lamp. 10.The method for manufacturing a semiconductor substrate according toclaim 9, wherein the planarization treatment includes etching treatment.11. The method for manufacturing a semiconductor substrate according toclaim 8, wherein a time of irradiation with the light from the flashlamp is 10 μs or more.
 12. The method for manufacturing a semiconductorsubstrate according to claim 8, wherein the light from the flash lamphas a continuous spectrum in a wavelength range from 400 nm to 700 nm.13. The method for manufacturing a semiconductor substrate according toclaim 8, wherein the flash lamp is a xenon lamp.
 14. The method formanufacturing a semiconductor substrate according to claim 8, wherein atemperature of the substrate having the insulating surface is kept at300° C. or higher during the irradiation with the light from the flashlamp.
 15. A method for manufacturing a semiconductor substrate,comprising the steps of: forming an insulating layer over a surface of asingle crystal semiconductor substrate; irradiating a surface of theinsulating layer with ions to form a damaged region in the singlecrystal semiconductor substrate; disposing a surface of a substratehaving an insulating surface and the surface of the insulating layer incontact with each other to bond the substrate having the insulatingsurface and the single crystal semiconductor substrate to each other;performing heat treatment to divide the single crystal semiconductorsubstrate along the damaged region and to form a semiconductor layerover the substrate having the insulating surface; and irradiating asurface of the semiconductor layer with light from a flash lamp under acondition where the semiconductor layer is not melted, to repair adefect.
 16. The method for manufacturing a semiconductor substrateaccording to claim 15, further comprising the step of performingplanarization treatment on the semiconductor layer before or after theirradiation with the light from the flash lamp.
 17. The method formanufacturing a semiconductor substrate according to claim 16, whereinthe planarization treatment includes etching treatment.
 18. The methodfor manufacturing a semiconductor substrate according to claim 15,wherein a time of irradiation with the light from the flash lamp is 10μs or more.
 19. The method for manufacturing a semiconductor substrateaccording to claim 15, wherein the light from the flash lamp has acontinuous spectrum in a wavelength range from 400 nm to 700 nm.
 20. Themethod for manufacturing a semiconductor substrate according to claim15, wherein the flash lamp is a xenon lamp.
 21. The method formanufacturing a semiconductor substrate according to claim 15, wherein atemperature of the substrate having the insulating surface is kept at300° C. or higher during the irradiation with the light from the flashlamp.
 22. A method for manufacturing a semiconductor substrate,comprising the steps of: forming a first insulating layer over a surfaceof a single crystal semiconductor substrate; irradiating a surface ofthe first insulating layer with ions to form a damaged region in thesingle crystal semiconductor substrate; forming a second insulatinglayer over a surface of a substrate having an insulating surface;disposing a surface of the second insulating layer and the surface ofthe first insulating layer in contact with each other to bond thesubstrate having the insulating surface and the single crystalsemiconductor substrate to each other; performing heat treatment todivide the single crystal semiconductor substrate along the damagedregion and to form a semiconductor layer over the substrate having theinsulating surface; and irradiating a surface of the semiconductor layerwith light from a flash lamp under a condition where the semiconductorlayer is not melted, to repair a defect.
 23. The method formanufacturing a semiconductor substrate according to claim 22, furthercomprising the step of performing planarization treatment on thesemiconductor layer before or after the irradiation with the light fromthe flash lamp.
 24. The method for manufacturing a semiconductorsubstrate according to claim 23, wherein the planarization treatmentincludes etching treatment.
 25. The method for manufacturing asemiconductor substrate according to claim 22, wherein a time ofirradiation with the light from the flash lamp is 10 μs or more.
 26. Themethod for manufacturing a semiconductor substrate according to claim22, wherein the light from the flash lamp has a continuous spectrum in awavelength range from 400 nm to 700 nm.
 27. The method for manufacturinga semiconductor substrate according to claim 22, wherein the flash lampis a xenon lamp.
 28. The method for manufacturing a semiconductorsubstrate according to claim 22, wherein a temperature of the substratehaving the insulating surface is kept at 300° C. or higher during theirradiation with the light from the flash lamp.